Unless potentially elaborate precautions are taken, electrostatic charges build up whenever non-conducting objects rub. Usually electrostatic charges dissipate harmlessly, but if they happen to discharge through an IC they can render the IC permanently non-functional. If an IC such as a CMOS IC is too sensitive to electrostatic discharge, then routine handling of the IC, or of circuit boards containing it, can destroy it.
One of the common methods used to evaluate the electrostatic discharge protection of an IC is the human body model, which is defined in MIL-STD 883C METHOD 3015.6. This evaluation method requires the discharge of a 100 pF capacitor, typically charged to 2000 volts, through a 1500 ohm resistor into one terminal of an IC under test, while grounding some other terminal of the IC. The higher the voltage that can be discharged through the IC without causing its functional failure, then the better its ESD protection. Other methods used for evaluating ESD protection are the machine model and the charged device model.
Various structures have been fabricated as part of CMOS and CMOS-like ICs to protect them from the destructive effects of ESD. FIG. 1 shows a circuit diagram that is typical of prior-art protection circuits. ICs typically have numerous input and output terminals, as well as some terminals that are combination input/output (I/O) terminals. FIG. 1 shows a generic ESD protection circuit for one input terminal and one output terminal of a CMOS IC built using a P-type substrate, which is connected to VSS and in which the N-channel transistors are fabricated. N-type wells, connected to VDD, are fabricated in substrate and the P-channel transistors are fabricated within these N-type wells. Input terminal T1 is protected by diodes D1 and D2, which are large-area diodes between T1 and power supply rails 101 and 102 for VSS and VDD respectively.
FIG. 1 also shows a typical prior-art output protection circuit. This circuit can be considered to include the parasitic diodes D3 and D4 which exist between output terminal T2 and power supply rails 101 and 102 respectively, and which are formed parasitically at the junctions of the drain diffusions of transistors N2 and P2 respectively. Transistors N2 and P2 form the output driver for output terminal T2. Also, FIG. 1 shows the parasitic well-to-substrate diode D5 between the VDD and VSS supply rails 102 and 101, which is formed at the edges of the N-well diffusions, which surround all P-channel transistors on the IC. FIG. 5 is a cross-sectional view of transistors N2 and P2, for the case of an P-substrate CMOS process. FIG. 5 shows where parasitic diodes D3 and D4 are formed, and the contribution of the N-type well surrounding P2 to forming parasitic diode D5. In contrast to parasitic diodes D3, D4, and D5, diodes D1 and D2 are intentionally included in the IC layout for ESD protection.
The level of ESD protection of an IC is measured by applying ESD transients between any two terminals of the IC. For example, if in FIG. 1 a positive pulse is applied to output terminal T2 with respect to input terminal T1 then, because there is no direct current path between these two terminals, the ESD energy will find the path of least resistance. This could be the path from output terminal T2 through resistor R2, then through N-channel transistor N2 via breakdown from drain to source or via breakdown from drain to substrate, then from the substrate to the VSS rail 101, and then through diode D1 to the input terminal T1. Alternatively, the path of least resistance could be through diode D4 to the VDD rail 102, then via breakdown of diode D5, then through the VSS rail, and then through diode D1 to input terminal T1. In each of these paths, an avalanche-type breakdown of a reverse-biased P-N junction is involved.
In avalanche breakdown of a P-N junction under reverse-biased voltage conditions, free carriers passing through the P-N junction gain enough energy from the electric field that is created by the voltage difference across the P-N junction that when they collide with covalent bonds in the lattice of the crystalline silicon they break the bonds. Breaking covalent bonds frees additional carriers, which likewise gain energy from the electric field, collide with covalent bonds, and free more carriers. This is much like an avalanche in which a small amount of snow high on a mountain starts moving and results in larger amounts of snow moving as the avalanche comes down the mountain. Just as a snow avalanche leaves most of the mountain's snow cover intact, avalanche P-N junction breakdown is typically localized to a small region with the largest electric field. This localization effect typically means that the current density, or current per unit area, occurring during avalanche breakdown is very high, which can lead to localized heating, which can melt portions of the crystalline silicon lattice or allow dopant atoms to migrate within the crystal, which can create a permanent functional failure of the IC. This localization effect typically means that the amount of current that can flow through a P-N junction under breakdown without permanent damage is orders of magnitude smaller than the amount of current that the same P-N junction can carry without damage when it is forward-biased.
In the prior art, the level of ESD protection is typically limited to the amount of energy that the weakest breakdown mechanism on the IC can handle without damage. In a typical commercial CMOS IC, the path mentioned first in the above discussion of FIG. 1 usually has a lower breakdown voltage, and thus offers the path of least resistance. Whenever an ESD transient traveling this path has too much energy, a destructive failure occurs, typically around the drain-to-gate area of transistor N2, due to localized heating during avalanche breakdown. Much of the prior art focuses on either improving the layout of transistor N2 together with resistor R2, or on improving transistor N2's drain junction doping profile to allow for larger ESD transients to be accommodated non-destructively during avalanche breakdown and snapback.
Other prior art has used a parasitic SCR structure (shown in FIG. 2) between the VDD and VSS rails, in which the breakdown voltage of the parasitic SCR is low. This technique attempts to provide a path of less resistance than the path through the drain of transistor N2. A good summary of this technique is provided in a paper by L. R. Avery, "A review of electrostatic discharge mechanisms and on-chip protection techniques to ensure device reliability", Journal of Electrostatics, 24 (1990), pp. 111-130.
Other prior art by Guggenmos and Holzner, "A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stress", 1991 EOS/ESD Symposium Proceedings, pp. 74-81 shows the use of an N-channel transistor N3 (shown in FIG. 3), whose drain is connected to VDD rail 102 and whose gate and source are connected to VSS rail 101 Transistor N3 operates in the drain avalanche breakdown and snapback mode, thus providing a current path from VDD to VSS.
Other prior art by Puar, "Input Protection Device for Integrated Circuits", U.S. Pat. No. 4,786,956, shows the use of an N-channel transistor whose drain is connected to the input terminal, whose source is connected to VSS and whose gate is connected to the substrate through a resistor (see column 3, lines 38-54. Like the present invention, the circuit path is provided that is intended to carry the ESD discharge without breakdown. It differs from the present invention, however, in that it requires one protection circuit per input pin, that it uses an N-channel transistor as the switching component that makes or breaks the path, and that the switching transistor is turned on via capacitive coupling from the ESD voltage on the drain of the N-channel transistor to its gate. In contrast, the present invention requires one protection circuit per each pair of VDD and VSS power supply rails, uses a P-channel transistor as the switching component, and turns on the switching component by direct coupling of the ESD pulse.
Other prior art by Keller is discussed in Puar's '956 patent column 1, line 65 to column 3, line 23. This prior art is suitable to protect input terminals only because of the high series resistance associated with resistor RA of FIG. 2 of Puar '956. Also, this prior art depends on breakdown mechanisms both in diode JA and transistor QA of the same Figure.
All the above-mentioned prior art techniques, other than Puar '956, have the limitation that they mechanisms on parasitic paths to conduct the ESD transient current. One limit to ESD protection that is inherent in depending on junction breakdown mechanisms is that, because of the localization effect of avalanche breakdown and its associated high current density and heat, typically the amount of current that can flow through a P-N junction under breakdown without permanent damage is orders of magnitude smaller than the amount of current that the same P-N junction can carry without damage when it is forward-biased. Another limit to ESD protection that is inherent in depending on junction breakdown mechanisms is that the breakdown voltage of the different devices is a function of the underlying processing technology used to fabricate the IC. What may be the path of least resistance on an IC fabricated using one technology may be different than the path of least resistance on an IC fabricated on another technology, even for similar or identical IC layouts, which complicates the task of engineering an effective ESD protection circuit. Thus there is a need for an ESD protection mechanism that avoids P-N junction breakdown.